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Home > PCI-Express

PCI-Express is intended to be used as a local bus only. Due to it being based on the existing PCI system, cards and systems can be converted to PCI-Express by changing the physical layer only – existing systems could be re-booted on PCI-Express and never even know it. The higher speeds on PCI-Express allow it to replace almost all existing internal buses, including AGP and PCI, and Intel envisions a single PCI-Express controller talking to all external devices, as opposed to the northbridge/ southbridge solution in current machines.

PCI-Express is not, however, fast enough to be used as a memory bus. In this respect it is at a distinct disadvantage to the similar HyperTransport which can be used for this role as well. In addition PCI-Express does not offer the flexibility of the InfiniBand system, which has similar performance, but can be used for both internal and external buses.

PCI-Express appears, at the time of writing in 2004, to be well on its way to becoming the new backplane standard in personal computers. High-end graphics cards from both ATI Technologies and nVidia have recently been converted from AGP to PCI-Express, which may be the incentive needed for other companies and devices to follow suit.

1 Hardware protocol

A connection between any two PCI-Express devices is known as a Link. Links are composed of 1, 2, 4, 8, 12, 16, 24 or 32 Lanes. When transmitting a packet on a Link, each byte is sent down a consecutive Lane.

Each Lane has a pair of transmit wires and a pair of receive wires which use differential signalling at 2.5Gbps. The 8B/10B encoding used on the Lane makes the data bandwidth effectively 250MB/s in each direction. Thus a 16x graphics card can receive 4GB/s and transmit 4GB/s simultaneously.

2 Form factors

PCI Express is specified for regular cards, low height cards, miniExpress cards, ExpressCards ( PCMCIA form factor) and AdvancedTCA (a replacement for CompactPCIA CompactPCI system is a 3U or 6U Eurocard based industrial computer, where all boards are connected via a passive PCI backplane. The pin assignments of the connectors are documented in standards, published by the organisation PICMG US and PICMG Europe.)

3 External links

• Creating a Third Generation I/O Interconnect (PDF)
• Intel Developer Network for PCI Express Architecture
• Ars Technica introduction to PCI Express

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