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One important feature was the register file of 16 registers of 16 bits each. Using the SEP instruction, you could select any of the 16 registers to be the program counter. Using the
SEX instruction, you could select anyof the 16 bit registers to be the index register. Register R0 had the special use of holding the memory address for the built in DMA controller.
The processor had 5 special I/O lines. There was a single Q output that could be set with the SEQ instruction and reset with the REQ instruction. There were four external flag inputs: EF1, EF2, EF3, EF4 and there were 8 dedicated branch instructions to conditionally branch based on the state of those input lines. The EF and Q lines were typically overused on RCA 1802 based computers because of their favorable handling. It was typical for the Q line to drive a status LED, a cassete interface, an RS-232 interface, and the speaker. This meant that the user could hear RS-232 and cassette data being transmitted.
The processor did not have standard subroutine CALL immediate and RET instructions, though they could be emulated. The register file made possible some interesting subroutine call and return mechanisms, though they were better suited to small programs than general purpose coding. A few commonly used subroutines could be called quickly by keeping their address in one of the 16 registers; the SEP instruction was used to call a subroutine pointed to by one of the 16 bit registers and RET to return. Before a subroutine returned, it jumped to the location immediately preceding its entry point so that after the RET instruction returned control to the caller, the register would be pointing to the right value for next time. An interesting variation of this scheme was to have two or more subroutines in a ring so that they were called in round robin order. Tricks like this were used in the horizontal refresh interrupt to reprogram the scan line address to repeat each scan line 4 times for the video controller. Computed subroutine calls were no problem because all CALL instructions were indexed (some processors only had CALL immediate).
Clock cycle efficiency was poor. 8 clock cycles made up one machine cycle. Most instructions took two machine cycles to execute.
The companion 1861 graphics controller chip used the build in
DMA controller to display bit mapped graphics. This chipcould display 64 pixels wide by 128 pixels high, though by reloading the R0 register, the resolution could be reduced to 64x64 or 64x32 to use less memory or to make square pixels. Since the frame buffer was similar in size to the memory size, it was not unusual to display your program/data on the screen allowing you to watch the computer think. Programs which ran amuck and accidentally overwrote themselves could be spectacular. Although the faster version of 1802 could operate at 5Mhz (at 5V, faster at 10V), it was usually operated at 3.58Mhz/2 to suit the requirements of the 1861 chip which gave a speed of a little over 100,000 instructions per second.
The built in DMA was typically used to load or view program memory, depending on the state of the write enable switch, after the processor had been reset but was held in a special wait state.
A number of early computers such as the COSMAC ELF, ELF II, and SuperELF as well as the RCA STUDIO II video game (one of the first to use bitmapped graphics).
The 1802 was also availible fabricated in Silicon on Sapphire which gives it the radiation resistance necessary for space applications and the 1802 was used in the Voyager, Viking, and Galileo spacecraft.
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